The invention relates to a design for a semiconductor memory device, and more particularly, to a semiconductor memory device operating with a test voltage received through an external pad in a burn-in test mode.
Generally, semiconductor memory devices including a double data rate synchronous DRAM (DDR SDRAM) undergo several test modes before production. Among these test modes, a burn-in test mode is a test mode that screens weak memory cells by applying a stress to memory cells storing data. The memory cells screened through the burn-in test mode can be replaced with redundancy cells in the subsequent process, thus fabricating high-quality semiconductor memory devices.
FIG. 1 is a circuit diagram of a conventional memory cell.
Referring to FIG. 1, a memory cell includes a cell transistor TR and a cell capacitor C.
The cell transistor TR forms a source-drain path between a bit line BL and the cell capacitor C, and has a gate connected to a word line WL to receive a back bias voltage VBB. Thus, when the word line WL is enabled, the cell transistor TR serves to transfer data between the cell capacitor C and the bit line BL.
The cell capacitor C is connected between the cell transistor TR and a cell plate voltage (VCP) terminal. Thus, the cell capacitor C serves to store data transferred through the cell transistor TR.
Meanwhile, the burn-in test mode is a test mode that applies a stress to a semiconductor memory device. That is, a pumping voltage applied to the word line WL, a precharging voltage applied to the bit line BL, a back bias voltage VBB, and a cell plate voltage VCP in the burn-in test mode are higher than those in a normal mode. In this way, a stress is applied to the memory cell. In the normal mode, the precharging voltage and the cell plate voltage VCP have half the voltage level of a core voltage.
In this way, higher voltages are applied in the burn-in test mode than in the normal mode. These high voltages are generally input through external pads. Since the aim of the burn-in test mode is to apply the stress to the memory cell, an internal voltage generator provided in the semiconductor memory device maintains a disabled state.
FIG. 2 is a block diagram for explaining external pads used in the burn-in test mode. Not all pads used in the normal mode are used in the burn-in test mode. Instead, a minimal number of pads are used.
Referring to FIG. 2, the semiconductor memory device includes first to fourth banks 210A to 210D, a wafer burn-in (WBI) pad 230, a test voltage supply pad 250, an address pad 270, and a power supply pad 290.
Each of the first to fourth banks 210A to 210D includes a plurality of memory cells for storing data.
The WBI pad 230 receives a burn-in test signal TM_WBI for entering a burn-in test mode, and the semiconductor memory device determines whether to enter the burn-in test mode according to the burn-in test signal TM_WBI. The burn-in test signal TM_WBI is input through a sixth pad 6.
The test voltage supply pad 250 receives a voltage for applying the stress to the memory cell. The first pad 1 receives a pumping test voltage TM_VPP higher than a pumping voltage in the normal mode, and the second pad 2 receives a core test voltage TM_VCORE higher than a core voltage in the normal mode. The third and fourth pads 3 and 4 receive first and second test voltages TM_V1 and TM_V2 to be used in the test mode, and the fifth pad 5 receives a back bias test voltage TM_VBB lower than the back bias voltage VBB in the normal mode.
The address pad 270 receives signals corresponding to internal commands of the semiconductor memory device and includes seventh to ninth pads 7 to 9. That is, the semiconductor memory device can perform eight internal operations according to first to third test mode signals TM1 to TM3 input through the seventh to ninth pads 7 to 9. The burn-in test mode can be divided into three cases. The semiconductor memory device can perform the eight internal operations according to the three cases.
The power supply pad 290 includes a tenth pad 10 for receiving a ground voltage VSS and an eleventh pad 11 for receiving an external power supply voltage VDD.
The burn-in test mode will be described below with reference to FIGS. 1 and 2. The burn-in test mode can be divided into three cases. For reference, the first and second test voltages TM_V1 and TM_V2 input through the third and fourth pads 3 and 4 may be the core test voltage TM_VCORE and the ground voltage VSS according to the test mode, respectively.
The first burn-in test mode corresponds to a case where the pumping test voltage TM_VPP is applied to the word line WL. In this case, the stress due to the pumping test voltage TM_VPP higher than in the normal mode is applied to the gate of the cell transistor TR.
The second burn-in test mode corresponds to a case where the ground voltage VSS input through the third pad 3 is applied to an input terminal of the cell capacitor C being a storage node, that is, a lower electrode of the capacitor, and the core test voltage TM_VCORE input through the fourth pad 4 is applied to the cell plate voltage (VCP) terminal, that is, an upper electrode of the capacitor. In this case, a higher potential difference is generated, compared to a logic low data in the normal mode, on both terminals of the cell capacitor C.
The third burn-in test mode corresponds to a case where the core test voltage TM_VCORE input through the third pad 3 is applied to an input terminal of the cell capacitor C, and the ground voltage VSS input through the fourth pad 4 is applied to the cell plate voltage (VCP) terminal. In this case, like the second case, a higher potential difference is generated, compared to a logic high data in the normal mode, on both terminals of the cell capacitor C.
The first burn-in test mode must precede the second burn-in test mode and the third burn-in test mode. That is, the first test voltage TM_V1 input through the third pad 3 is applied to the input terminal of the cell capacitor C through the bit line BL.
Meanwhile, the conventional semiconductor memory device uses eleven external pads to perform the burn-in test mode. That is, a test equipment must allocate at least eleven test pins per the semiconductor memory device in order to perform the burn-in test mode. If the test equipment has one hundred ten test pins, it can test eleven semiconductor memory devices at a time. Generally, if the number of semiconductor memory device that can be tested at a time increases, a total test time necessary to perform the test operation is reduced. In other words, if the number of the pads used in the test mode decreases, a total test time can be reduced, which means the reduction of the product cost.